• * J. Kapustinsky: Overview of FVTX detector design
  • o HDI length ~12cm
  • o Sensors are AC coupled with internal 1.5M biasing resistor.
    • + This will lead to ~13% increase in noise (T. Zimmerman)
  • o Power consumption is larger then initially expected.
    • + There is a desire to look at reducing the power consumption if possible.
    • + Current estimates: 150uW front end, 200uW Digital, 75 uW per serial pair
  • o Would like a the power up state of the chip to be stable and reproducible.
  • o Comment on preliminary electrical connections for FPHX chip
    • + For ISET, need filter cap to GND (T. Zimmerman/J. Hoff)
    • + For Substrate connection, no resistor to ground (T. Zimmerman/J. Hoff)
  • o Clarified distance from FPHX to ROC as ~30cm, or 3nsec round trip time
  • o Expected signal size is 5 times threshold
  • o Need to think about baseline restoration and specify what it should be.
  • o There should be sufficient capacitance for high rate conditions
  • o 200 MHz clock
    • + Bussed clock, will it work?
    • + Need to keep stubs as short as possible
    • + Follow LVDS bus design rules
    • + Implement impedance control connector.
• * T. Zimmerman: Analog Overview
  • o Leakage current compensation is programmable, 0-50 nA.
  • o Gain programmable: 50, 67, 100 or 200 mV/fC
  • o Nominal peaking time, 60nSec
  • o Currently 2 test inputs, one analog, one digital.
  • o Fall time is programmable, need to understand the limits.
  • o FPHX chip uses different comparator circuit then FPIX chip to reduce power consumption.
    • + Should run simulation to see if there is a spike when comparator turns on.
  • o Question about large pulses:
    • + How soon a second small pulse would be observed- Simulations?
    • + Large pulses might be observed in multiple BCOs
    • + The comparator disconnect offers some hysteresis.
    • + concerns about firing on noise.
• * J. Hoff: Digital Design Overview
  • o Chip pad assignments still have some flexibility if there is desire for change.
  • o Based on earlier discussions, there is no such thing as a truncated event
    • + On large event, phase count stops, all hits are output
    • + Hits in follwoing BCO are lost.
    • + 128 hit event would lose next 6 BCOs
    • + Large events will fill 32 hit deep event
    • + Fifo filled on 48 hit event?
    • + Bit to indicate current word is last word
    • + Last word may be lost on large event?
  • o Discussion on implementing a FIFO reset, however, the implications need to be understood.
  • o Serial clock is 20 * BCO and implemented on ROC. Verify that ACTEL chip can do this.
  • o Question on how sensitive serial clock is to jitter.
  • o Serial output:
    • + Two serializers
    • + If one serial line, 40 clocks to output two words
    • + If two serial lines, 20 clocks to output 2 words.
    • + 20 bit words to each serial line, no broken word like in FPIX chip
    • + programmable drive current possible? Yes
  • o Slow control
    • + 32 bit word. 7 bit header, 5 bit ID, 5 bit register, 3 bit command, 8 bit data, 4 bit trailer
    • + All commands generate a read of register if chip/register ID is not wild card
  • o No power on reset, final turn on will be indeterminate.
  • o Possibility of smart core reset
  • o Need guidance on:
    • + smart core reset
    • + power
    • + programmable LVDS drivers
    • + LVDS receivers.
• * General Issues:
  • o Question about ownership of the mask and how the PO will be issued. Let the lawyers work on this.
  • o Making April submission date critical. Issue of rolling furloughs came up.
• * Follow up meeting March 6, 2008